Work function adjustment with the implant of lanthanides

ABSTRACT

Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 13/855,457,filed Apr. 02, 2013.

Application Ser. No. 13/855,457 is a continuation of application Ser.No. 12/979,908 filed Dec. 28, 2010 (TI-62452B), (now U.S. Pat. No.8,409,943)

Application Ser. No. 12/979,908 is a continuation of application Ser.No. 11/737,856 filed Apr. 20, 2007, now U.S. Pat. No. 7,858,459(TI-62452A).

Application Ser. No. 12/979,908 is a continuation-in-part of applicationSer. No. 12/965,528 filed Dec. 10, 2010, which is a continuation ofapplication Ser. No. 12/255,500 filed Oct. 21, 2008, which is a divisionof application Ser. No. 11/694,662 filed Mar. 30, 2007 (TI-63191).

Application Ser. No. 12/979,908 is a continuation-in-part of applicationSer. No. 11/590,133 filed Oct. 31, 2006 (TI-63477).

Application Ser. No. 12/979,908 is a continuation-in-part of applicationSer. No. 12/886,863 filed Sep. 21, 2010, which is a division ofapplication Ser. No. 11/741,476 filed Apr. 27, 2007 (TI-62451), (nowU.S. Pat. No. 7,799,699).

Application Ser. No. 12/979,908 is a continuation-in-part of applicationSer. No. 12,731,900 filed Mar. 25, 2010, which is a division ofapplication Ser. No. 11/934,250 filed Nov. 2, 2007 (now U.S. Pat. No.8,629,021).

The entireties of all of the above applications are hereby incorporatedby reference.

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor devices andmore particularly to NMOS transistor devices and fabrication methods formaking the same.

Field effect transistors (FETs) are widely used in the electronicsindustry for switching, amplification, filtering, and other tasksrelated to both analog and digital electrical signals. Most common amongthese are metal oxide semiconductor field effect transistors (MOSFETs),wherein a gate electrode is energized to create an electric field in achannel region of a semiconductor body, by which electrons are allowedto travel through the channel between a source region and a drain regionof the semiconductor body. The source and drain regions are typicallyformed by adding dopants to targeted regions on either side of thechannel. A gate dielectric or gate oxide is formed over the channel, anda gate electrode or gate contact is formed over the gate dielectric. Thegate dielectric and gate electrode layers are then patterned to form agate structure overlying the channel region of the substrate.

In operation of the resulting MOS transistor, the threshold voltage (Vt)is the gate voltage value required to render the channel conductive byformation of an inversion layer at the surface of the semiconductorchannel. Complimentary MOS (CMOS) devices have become widely used in thesemiconductor industry, wherein both n-channel and p-channel (NMOS andPMOS) transistors are used to fabricate logic and other circuitry. Forenhancement-mode (e.g., normally off) devices, the threshold voltage Vtis positive for NMOS and negative for PMOS transistors. The thresholdvoltage is dependent upon the flat-band voltage, where the flat-bandvoltage depends on the work function difference between the gate and thesubstrate materials, as well as on surface charge.

The work function of a material is a measure of the energy required tomove an electron in the material outside of a material atom from theFermi level, and is usually expressed in electron volts (eV). For CMOSproducts, it is desirable to provide predictable, repeatable, and stablethreshold voltages (Vt) for the NMOS and PMOS transistors. To establishVt values, the work functions of the PMOS and NMOS gate contact and thecorresponding channel materials are independently tuned or adjustedthrough gate and channel engineering, respectively.

Gate stack engineering is employed to adjust the work function of thegate contact materials, where different gate work function values areset for PMOS and NMOS gates. The need to independently adjust PMOS andNMOS gate work functions has made polysilicon attractive for use as agate contact material in CMOS processes, since the work function ofpolysilicon can be easily raised or lowered by doping the polysiliconwith p-type or n-type impurities, respectively. The PMOS polysilicongates are typically doped with p-type impurities and NMOS gatepolysilicon is doped with n-type dopants, typically during implantationof the respective source/drain regions following gate patterning. Inthis way, the final gate work functions are typically near the Siconduction band edge for NMOS and near the valence band edge for PMOS.The provision of dopants into the polysilicon also has the benefit ofincreasing the conductivity of the gate electrode. Polysilicon has thusfar been widely used in the fabrication of CMOS devices, wherein thegate engineering provides a desired gate electrode conductivity (e.g.,sheet resistance value) by conventional tuning (e.g., implants), and thethreshold voltage fine tuning is achieved by tailoring the channeldoping level through the Vt adjust implants.

FIG. 1 illustrates a conventional CMOS fabrication process 10 beginningat 12, in which front end processing is performed at 14, including wellformation and isolation processing. At 16 and 18, channel engineering isperformed (e.g., Vt adjust, punch-thru, and channel stop implants) forPMOS and NMOS regions, respectively. A thin gate dielectric and anoverlying polysilicon layer are formed at 20 and 22, respectively, andthe polysilicon is patterned at 24 to form gate structures for theprospective NMOS and PMOS transistors. The gate structures are thenencapsulated at 26, typically through oxidation, and highly-doped drain(HDD) implants are performed at 28 to provide p-type dopants toprospective source/drains of the PMOS regions and n-type dopants tosource/drains of the NMOS regions, using the patterned gate structuresand isolation structures as an implantation mask. Sidewall spacers arethen formed at 30 along the lateral sidewalls of the gate structures.

At 32, the PMOS source/drain regions and the PMOS polysilicon gatestructures are implanted with p-type dopants to further define the PMOSsource/drains, and to render the PMOS gates conductive. Similarly, theNMOS source/drain regions and the NMOS polysilicon gate structures areimplanted at 34 with n-type dopants, further defining the NMOSsource/drains and rendering the NMOS gates conductive. Thereafter, thesource/drains and gates are silicided at 36 and back end processing(e.g., interconnect metalization, etc.) is performed at 38, before theprocess 10 ends at 40. In the conventional process 10, the channelengineering implants at 16 and 18 shift the Vt of the PMOS and NMOSchannel regions, respectively, to compensate for the changes in the PMOSand NMOS polysilicon gate work functions resulting from the source/drainimplants at 32 and 34, respectively. In this manner, the desired workfunction difference between the gates and channels may be achieved forthe resulting PMOS and NMOS transistors, and hence the desired thresholdvoltages.

The gate dielectric or gate oxide between the channel and the gateelectrode is an insulator material, typically SiO₂, nitrided SiO₂, orother dielectric, that operates to prevent current from flowing from thegate electrode into the channel when a voltage is applied to the gateelectrode. The gate dielectric also allows an applied gate voltage toestablish an electric field in the channel region in a controllablemanner. Continuing trends in semiconductor product manufacturing includereduction in electrical device feature sizes (scaling), as well asimprovements in device performance in terms of device switching speedand power consumption. MOS transistor performance may be improved byreducing the distance between the source and the drain regions under thegate electrode of the device, known as the gate or channel length, andby reducing the thickness of the layer of gate dielectric that is formedover the semiconductor surface.

However, there are electrical and physical limitations on the extent towhich SiO2 gate dielectrics can be made more thin. These include gateleakage currents tunneling through the thin gate oxide, limitations onthe ability to form very thin oxide films with uniform thickness, andthe inability of very thin SiO2 gate dielectric layers to prevent dopantdiffusion from the gate polysilicon into the underlying channel.Accordingly, recent scaling efforts have focused on high-k dielectricmaterials having dielectric constants greater than that of SiO2, whichcan be formed in a thicker layer than scaled SiO2, and yet which produceequivalent field effect performance. A thicker high-k dielectric layercan thus be formed to avoid or mitigate tunneling leakage currents,while still achieving the required electrical performance equivalent(e.g., capacitance value) to a thinner SiO2.

It has also been proposed to utilize hafnium-based high-k dielectricmaterials in combination with a lanthanide series metal to lower thework function of metal gates. The lanthanide series metal is provided asa distinct surface layer over the high-k dielectric material. Thisproposal, however, may decrease the overall equivalent oxide thickness(EOT) of the layer of gate oxide.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to themore detailed description that is presented later.

In one embodiment, the invention is directed to a method of fabricatinga transistor, the method comprising forming a gate dielectric over asemiconductor body. A gate electrode is formed over the gate dielectric,and a lanthanide series material is introduced into the gate electrode.The lanthanide series material is then driven subsequently into the gatedielectric from the gate electrode. Lastly, source/drain regions areformed in the semiconductor body on opposing sides of the gate, therebydefining a channel region therebetween. In one embodiment, the gateelectrode is a silicon material, in which case, a silicidation may thenbe employed, for example, fully siliciding the gate electrode.

In another embodiment of the invention, a transistor formation methodcomprises forming a gate dielectric that contains a lanthanide seriesmaterial over a semiconductor body. A silicon based gate electrode isthen formed over the gate dielectric, followed by the formation ofsource/drain regions in the semiconductor body on opposing sides of thegate electrode. In one embodiment, the gate dielectric comprises ahigh-k dielectric material. In another embodiment, the gate dielectriccomprises a silicon oxide interface layer, with a high-k dielectricformed thereover. The lanthanide series material, in such an example,extends throughout the high-k dielectric and does not extend into thesilicon oxide interface layer.

According to yet another embodiment of the invention, a transistorstructure is provided, wherein a gate dielectric material containing alanthanide series material resides over a semiconductor body. Thelanthanide series material in the gate dielectric resides in a topportion thereof and does not extend down to the interface of the gatedielectric and the semiconductor body. The transistor further includes asilicon based gate electrode overlying the gate electrode. Source/drainregions reside in the semiconductor body on opposing sides of the gate.In another embodiment, the silicon based gate electrode is silicided,for example, fully silicided with nickel.

The following description and annexed drawings set forth in detailcertain illustrative aspects and implementations of the invention. Theseare indicative of but a few of the various ways in which the principlesof the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (Prior Art) is a simplified flow diagram illustrating aconventional polysilicon gate CMOS fabrication process including channelengineering for both PMOS and NMOS transistors;

FIG. 2 is a flow diagram illustrating an exemplary method of fabricatinga transistor in accordance with an aspect of the present invention;

FIGS. 3A-3F are partial side elevation views in section illustrating anexemplary transistor undergoing processing in accordance with anembodiment of the invention at various stages of fabrication; and

FIG. 4 is a flow diagram illustrating an exemplary method of fabricatinga transistor in accordance with another aspect of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

One or more implementations of the present invention will now bedescribed with reference to the attached drawings, wherein likereference numerals are used to refer to like elements throughout, andwherein the illustrated structures are not necessarily drawn to scale.The invention relates to a method and related transistor device. In oneembodiment of the invention, a lanthanide series material isincorporated into a top portion of a gate dielectric, and a siliconbased gate electrode is formed thereover. In another embodiment of theinvention, the gate electrode is fully silicided, for example, with anickel silicide. The incorporation of the lanthanide series materialinto the gate dielectric advantageously provides for a reduction in thework function in an NMOS type transistor device.

Referring initially to FIGS. 2-3F, an exemplary method 50 is illustratedin FIG. 2 for fabricating a transistor structure for an NMOS transistor,for example, in accordance with one embodiment of the present invention.FIGS. 3A-3F illustrate various exemplary implementations of portions ofthe method 50 relating to creation of a transistor with a reduced workfunction. While the exemplary method 50 is illustrated and describedbelow as a series of acts or events, it will be appreciated that thepresent invention is not limited by the illustrated ordering of suchacts or events. For example, some acts may occur in different ordersand/or concurrently with other acts or events apart from thoseillustrated and/or described herein, in accordance with the invention.In addition, not all illustrated steps may be required to implement amethodology in accordance with the present invention. Further, themethods according to the present invention may be implemented inassociation with the formation and/or processing of structuresillustrated and described herein as well as in association with otherstructures and devices not illustrated.

The method 50 begins at 52 in FIG. 2, wherein front end processing isperformed at 54. Any front end processing may be performed within thescope of the invention, wherein the processing at 54 may include, forexample, formation of n and p wells using diffusion, implantation, orother suitable processing steps, as well as formation of isolationstructures in field regions of a device wafer using LOCOS, STI, or anysuitable isolation processing. While the figures provided show use ofLOCOS type field-oxide (FOX), type isolation structures, shallow trenchisolation (STI) or other type isolation structures may also be employedand are contemplated by the present invention. The methods and devicesof the invention may be implemented using any type of semiconductorbody, including but not limited to bulk semiconductor wafers (e.g.,silicon), epitaxial layers formed over a bulk semiconductor, SOI wafers,etc. At 56 channel engineering may be performed, for example, thresholdvoltage adjustment implants, punch-through implants, etc.

At 58, a gate dielectric is formed in an NMOS region using any suitablematerials, material thicknesses, and processing steps, including asingle thermal oxidation or deposition or combinations thereof to form agate dielectric above the semiconductor body, which may be a singlelayer or multiple layers. The invention may be employed in conjunctionwith gate dielectric materials formed from nitrided SiO2, high-kdielectrics, including but not limited to binary metal oxides includingaluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2),lanthanide oxides (e.g., La2O3, Yb2O3), yttrium oxide (Y2O3), titaniumoxide (TiO2), as well as their silicates and aluminates; metaloxynitrides including aluminum oxynitride (AlON), zirconium oxynitride(ZrON), hafnium oxynitride (HfON), lanthanide oxynitrides (e.g., LaON,YbON), yttrium oxynitride (YON), as well as their silicates andaluminates such as ZrSiON, HfSiON, LaSiON, YSiON, etc.; andperovskite-type oxides including a titanate system material such asbarium titanate, strontium titanate, barium strontium titanate (BST),lead titanate, lead zirconate titanate, lead lanthanum zirconatetitanate, barium lanthanum titanate, barium zirconium titanate; aniobate or tantalate system material such as lead magnesium niobate,lithium niobate, lithium tantalate, potassium niobate, strontiumaluminum tantalate and potassium tantalum niobate; a tungsten-bronzesystem material such as barium strontium niobate, lead barium niobate,barium titanium niobate; and bi-layered perovskite system material suchas strontium bismuth tantalate, bismuth titanate and others.

In the examples illustrated and described herein, a single thermaloxidation is performed at 58 to create a thin gate dielectric oxide(e.g., a thermally grown silicon oxide) overlying the substrate in theNMOS region, followed by the formation of a high-k dielectric materialthereover. In one embodiment of the invention, the high-k dielectricmaterial comprises HfSiON and is formed by chemical vapor deposition(CVD) or ALD. Referring briefly to FIG. 3A as one illuminating example,an NMOS device area 302 includes a p-type substrate 304, in which ap-type well 306 is formed. The active area or moat region is defined inthis example as the region between the field-oxide isolation regions310. A thin oxide interface layer 312 and a high-k dielectric layer 314disposed thereover are illustrated as formed by a deposition process316.

Following gate dielectric formation at 58, the method 50 provides forgate fabrication indicated generally at 60, wherein FIG. 3B illustratesthe general gate electrode layer deposition at 320. In one embodiment ofthe invention, the gate electrode layer 318 comprises a silicon basedgate electrode. In one embodiment, the gate electrode layer comprises anamorphous silicon layer, and in another embodiment the gate electrodecomprises a polysilicon layer. Such layers may be formed via a CVDprocess, wherein for an amorphous layer a lower temperature of about520° C., for example, is employed, while for a polysilicon layer ahigher temperature of about 650° C., for example, is employed. In oneexample, the polysilicon or amorphous silicon layer has a thickness ofabout 800 Angstroms.

According to one embodiment of the invention, the method 50 of FIG. 2continues at 62 with an implant of a lanthanide series metal into thegate electrode layer, as illustrated in FIG. 3C at 322. Any suitableimplantation techniques and operational settings may be employed. Theimplant species comprises a lanthanide series metal and can include oneor more of lanthanum, cerium, praseodymium, neodymium, promethium,samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium,thulium, ytterbium, lutetium, or hafnium. While hafnium is not an actuallanthanide series element, for purposes of the present invention,hafnium is included herein. In one embodiment of the invention, theimplant energy is selected to be sufficient to drive dopant down near abottom interface of the gate electrode and the underlying gatedielectric, without such dopant reaching the gate dielectric during theimplant.

In one embodiment of the invention, the doping of the gate electrodewith the lanthanide series metal occurs in the NMOS region of thedevice, but not in the PMOS region. One way in which such a process maybe implemented is by forming an implant mask over the PMOS region priorto the implant at 62. This may be performed so that the lanthanideseries metal will operate to lower the work function in the resultingNMOS device in the NMOS region, and not impact the PMOS devices in thePMOS region, since the PMOS work function typically is not affected, oralternatively actions are taken to increase the PMOS device workfunction.

In one embodiment of the invention, the gate electrode layer may also beimplanted with oxygen, wherein the oxygen may operate to reduce adiffusion coefficient associated with the lanthanide series material inany subsequent anneal processes.

The method 50 then continues at 64 of FIG. 2 with an activation annealthat operates to activate the lanthanide series material into the gatedielectric. In one embodiment of the invention, the activation annealcomprises a spike anneal of short duration (e.g., 3 seconds or less) ata relatively high temperature (e.g., about 1060° C.). The activationanneal serves to cause at least some of the lanthanide series materialto diffuse from the overlying gate electrode layer 318 down into thegate dielectric layer 314. In one embodiment of the invention, theactivation anneal parameters are tailored to facilitate the lanthanideseries material to diffuse into a top portion of the gate dielectric,but not down to the interface of the gate dielectric and thesemiconductor body. For example, in one embodiment of the invention thelanthanide series material diffuses into the high-k dielectric layer314, but not down into the underlying interface dielectric layer 312illustrated in FIG. 3C.

In yet another embodiment of the invention, the activation anneal may beperformed with an ambient gas mixture comprising at least oxygen andnitrogen, wherein the oxygen may operate to reduce an amount ofdiffusion of the lanthanide series material during the anneal process.

While in the above example the lanthanide series metal was introducedinto the gate electrode by way of ion implantation, it should beunderstood that any manner of introducing such material therein may beemployed and is contemplated as falling within the scope of the presentinvention. For example, one alternative manner may dope the silicon gateelectrode material in-situ during the chemical vapor deposition of thesilicon gate material. In such an example, the gate electrode materialmay be deposited and then subsequently removed in the PMOS regions,followed by another gate electrode layer deposition for the PMOSregions.

Reaction of the implanted lanthanide series metal with the gatedielectric provides for a downward adjustment of the material workfunction, thereby tuning the threshold voltage of the resulting NMOStransistor. In one embodiment, the resultant work function of thefinished NMOS device is reduced to about 4.1 eV.

The gate electrode layer is then patterned at 66 to form the actual gateelectrode, as illustrated at 330 in FIG. 3D. Such patterning may beperformed via a dry plasma etch 330 using a hard mask 332, for example,resulting in substantially vertical sidewalls, in one embodiment. Asillustrated in FIG. 3D, the gate dielectric 312, 314 may also bepatterned at this time to expose the source/drain regions 334 of thesemiconductor body. Alternatively, however, the gate dielectric may beremoved at a later time.

The method 50 of FIG. 2 then continues at 68, 70 and 72, wherein offsetspacers, extension region implants, sidewall spacers, and source/drainimplants are performed in one embodiment to finish a first part of thetransistor structure. For example, as illustrated in FIG. 3E, offsetspacers 340 are first formed on lateral edges of the patterned gateelectrode 328, followed by extension region implants, wherein theresultant extension regions 342 are self-aligned with respect to theoffset spacers. Sidewall spacers 344 are then formed on the offsetspacers 340, after which a source/drain implant process 346 is performedto form the source/drain regions 348 in the semiconductor body. Asillustrated, the resultant source/drain regions 348 are self-alignedwith respect to the offset spacers 344.

The method 50 of FIG. 2 then continues with silicidation at 74, asillustrated at 349 in FIG. 3F, followed by backend processing at 76,wherein contacts are formed down to the completed device throughdielectric layers, followed by a plurality of metallization layers, asmay be appreciated. In one embodiment of the invention, the silicidationat 74 results in a full silicidation (FUSI) of the gate electrode 328,resulting in structure 350 comprising the fully silicided gate, andsilicided source/drain regions 352. For example, in one embodiment anickel layer having a thickness of about 500 Angstroms is deposited by asuitable process such as sputtering, followed by a first anneal of about360° C. for about 60 seconds to form Ni₂Si. The un-reacted nickel isthen removed using a wet chemical strip, for example, followed by asecond anneal of about 520° C. for about 30 seconds to form NiSi.

In accordance with another embodiment of the invention, a method 100 offorming a transistor structure is provided in the flow chart of FIG. 4.In the method 100, front end processing 54, channel engineering 56, gatedielectric formation 58, and gate electrode formation 60 may proceed ina normal fashion, after which the gate electrode is patterned at 102prior to an incorporation of lanthanide series material therein. Afterthe gate electrode patterning at 102, the lanthanide series metal isincorporated therein, for example, via implantation at 104. In oneembodiment of the invention, an implant mask may be employed at 104 toavoid the lanthanide implant from entering one or more undesired areas.The method then continues at 64 with an activation anneal that causesthe lanthanide series material to be driven down into the gatedielectric material. Further, in this embodiment the lanthanide seriesmetal enters a top portion of the gate dielectric, but does not extenddown to the interface between the gate dielectric and the underlyingsemiconductor body. The method 100 then continues on in a manner similarto that of FIG. 2.

Although the invention has been illustrated and described with respectto one or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the invention. Inaddition, while a particular feature of the invention may have beendisclosed with respect to only one of several implementations, suchfeature may be combined with one or more other features of the otherimplementations as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and the claims, such termsare intended to be inclusive in a manner similar to the term“comprising”.

What is claimed is:
 1. A method of forming a transistor, comprising:forming a gate dielectric over a semiconductor body, wherein the gatedielectric comprises a material in a top portion thereof that does notextend to an interface between the gate dielectric and the semiconductorbody, wherein the material is selected from the group consisting oflanthanum, cerium, praseodymium, neodymium, promethium, samarium,europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium,ytterbium, and lutetium; and forming a silicon gate electrode over thegate dielectric.
 2. The method of claim 1, further comprising fullysiliciding the gate electrode.
 3. The method of claim 2, wherein fullysiliciding the gate electrode comprises: forming a nickel layer over thegate electrode; and performing one or more thermal processes so as tofully react the silicon of the gate electrode with the nickel layer,thereby causing substantially the entire gate electrode to comprise anickel silicide.